The present invention relates generally to the field of memory devices and more specifically to the field of nonvolatile memory devices containing diode steering elements.
Three dimensional memories have memory cells located at numerous levels above a substrate. Each level includes a plurality of parallel first lines, such as word lines, extending in one direction. The first lines are vertically separated from a plurality of parallel second lines, such as bit lines, extending in a second direction. The first lines may extend perpendicular to the first lines. Cells are located between the first lines and second lines at the intersections of these lines. These memories are described, for example, in U.S. Pat. Nos. 5,835,396 and 6,034,882.
Another way of fabricating three-dimensional memory arrays uses “rail-stacks” as described in U.S. Pat. No. 6,420,215 and in U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000, which describes a memory employing antifuses where a diode is formed upon programming a particular bit. The previous designs only have one diode in series with a memory layer in each cell.